#ifdef DUET2

#include "usw/include/drv_common.h"
#include "usw/include/drv_enum.h"
#include "usw/include/drv_ftm.h"
#include "usw/include/drv_ser.h"
#include "usw/include/drv_chip_ctrl.h"



#undef DRV_DEF_C
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F

#ifdef DRV_DEF_C
	#error DRV_DEF_C has been defined
#endif

#ifdef DRV_DEF_M
	#error DRV_DEF_M has been defined
#endif

#ifdef DRV_DEF_D
	#error DRV_DEF_D has been defined
#endif

#ifdef DRV_DEF_F
	#error DRV_DEF_F has been defined
#endif

#ifdef DRV_DEF_E
	#error DRV_DEF_E has been defined
#endif

#ifdef DRV_DEF_SDK_D
	#error DRV_DEF_SDK_D has been defined
#endif

#ifdef DRV_DEF_SDK_F
	#error DRV_DEF_SDK_F has been defined
#endif

extern tables_info_t drv_tm_tbls_list[];

 /*DS ADDR*/
#define CTC_DS_ADDR(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbMode, TcamMem, Bus, Stats, ...) \
   static addrs_t RegName##_tbl_addrs_dt2[] = {__VA_ARGS__};

 /*DS LIST*/
#define CTC_DS_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbMode, TcamMem, Bus, Stats, ...) \
   { \
      SliceType, \
      OpType, \
      Entry, \
      0,      \
      Word*4, \
      SdbMode,    \
      SdbMode == 0? 0 : 1, \
      Bus,    \
      Stats,  \
      sizeof(RegName##_tbl_addrs_dt2)/sizeof(addrs_t), \
      0, \
      sizeof(RegName##_tbl_fields_dt2)/sizeof(fields_t), \
      EntryOffset*4, \
      TcamMem, \
      DRV_FEATURE_MODE_PER_CORE, \
      RegName##_t,\
      0, \
      RegName##_tbl_addrs_dt2, \
      RegName##_tbl_fields_dt2, \
   },

#define CTC_DS_INFO1(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
    { \
    #ModuleName, \
    #RegName, \
       RegAlias##_tbl_fields_name_dt2, \
    },

 /*Field Addr*/
#define CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, ...) \
  static segs_t RegName##_##FieldName##_tbl_segs_dt2[] = {__VA_ARGS__};

 /*Field Info*/
#define CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, ...) \
   { \
	  RegName##_##FieldName##_f,\
      Bits, \
      sizeof(RegName##_##FieldName##_tbl_segs_dt2) / sizeof(segs_t), \
      RegName##_##FieldName##_tbl_segs_dt2, \
   },

#define CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, ...) \
       { \
      #FullName, \
       },

#define CTC_FIELD_E_INFO() \
   { \
   },
#define CTC_FIELD_E_INFO1() \
     { \
     },

 /*DS Field List Seperator*/
#define CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
 }; \
 static fields_t RegName##_tbl_fields_dt2[] = {


#define DRV_DEF_C(MaxInstNum, MaxEntry, MaxWord, MaxBits,MaxStartPos,MaxSegSize)

 /* Segment Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...) \
        CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E()
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...) \
        CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#include "usw/include/drv_ds_dt2.h"
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* Field Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...)

#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName,FullName, Bits, ...) \
        CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E() CTC_FIELD_E_INFO()
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName,FullName, Bits, ...) \
        CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
fields_t dt2_fields_1st = {0,0,0,NULL
#include "usw/include/drv_ds_dt2.h"
};

#ifndef DRV_DS_LITE
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_DD
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E
#undef CTC_DS_SEPERATOR_INFO
 
#define CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
  }; \
  static fields_name_t RegName##_tbl_fields_name_dt2[] = {
 
   /* Field Name Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
          CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...) \
          CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
          CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName,FullName, Bits, ...) \
          CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E() CTC_FIELD_E_INFO1()
  
  fields_name_t dt2_fields_name = {NULL
#include "usw/include/drv_ds_dt2.h"
  };
#endif

#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* DS Address*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbMode, SER_R, Bus, Stats, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbMode, SER_R, Bus, Stats, ...) \
        CTC_DS_ADDR(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbMode, SER_R, Bus, Stats, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName,  Bits, ...)
#endif
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbMode, SER_R, Bus, Stats, ...) \
        CTC_DS_ADDR(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbMode, SER_R, Bus, Stats, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E()
#include "usw/include/drv_ds_dt2.h"
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* DS List*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#endif
#define DRV_DEF_E()

#define DRV_DEF_FIELD_E()
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
tables_info_t drv_dt2_tbls_list[] = {
#include "usw/include/drv_ds_dt2.h"
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,NULL,NULL}
};
#ifndef DRV_DS_LITE
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
        
#undef DRV_DEF_DD
#undef DRV_DEF_FIELD_E

     /* DS List name*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#endif
#define DRV_DEF_DD(ModuleName, InstNum, RegName, RegAlias,SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#define DRV_DEF_E() 
#define DRV_DEF_FIELD_E()


tables_name_t drv_dt2_tbls_name_list[] = {
#include "usw/include/drv_ds_dt2.h"
{NULL, NULL, NULL}
};
#endif

/*ECC Interrupt*/
#define DRV_ECC_F(...)  {__VA_ARGS__},



#define MCU0_MUTEX0_CPU_DATA   0x00080080
#define MCU0_MUTEX0_CPU_MASK   0x00080084
#define MCU0_MUTEX1_CPU_DATA   0x00080088
#define MCU0_MUTEX1_CPU_MASK   0x0008008C

#define MCU1_MUTEX0_CPU_DATA   0x00040080
#define MCU1_MUTEX0_CPU_MASK   0x00040084
#define MCU1_MUTEX1_CPU_DATA   0x00040088
#define MCU1_MUTEX1_CPU_MASK   0x0004008C



uint32 drv_dt2_enum[DRV_CONSTANT_MAX];

drv_mem_t drv_dt2_mem[DRV_FTM_MAX_ID];
uint32 drv_dt2_tcam_mem_map[] =
{
    FlowTcamTcamMem_t,           /*0*/
    LpmTcamTcamMem_t,            /*1*/
    IpeCidTcamMem_t,             /*2*/
    QMgrEnqTcamMem_t,            /*3*/
    FlowTcamAdMem_t,             /*4*/
    LpmTcamAdMem_t,              /*5*/
};

drv_ecc_intr_tbl_t drv_ecc_dt2_err_intr_tbl[] =
{
#include "usw/include/drv_ecc_intr_d2.h"
    {MaxTblId_t,0,0,0,0,0,0,0,0}
};

drv_ecc_sbe_cnt_t drv_ecc_dt2_sbe_cnt[] =
{
    {BufRetrvFirstFragRam_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvFirstFragRamSbeCnt_f},
    {BufRetrvLinkListRam_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvLinkListRamSbeCnt_f},
    {BufRetrvMsgParkMem_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvMsgParkMemSbeCnt_f},
    {BufRetrvPktMsgMem_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvPktMsgMemSbeCnt_f},
    {BufStoreChanInfo_t,BufStoreParityStatus_t,BufStoreParityStatus_bufStoreChanInfoSbeCnt_f},
    {BufStoreFreeListRam_t,BufStoreParityStatus_t,BufStoreParityStatus_bufStoreFreeListRamSbeCnt_f},
    {DmaDescCache_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaDescCacheSbeCnt_f},
    {DmaInfoMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaInfoMemSbeCnt_f},
    {DmaPktRxMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaPktRxMemSbeCnt_f},
    {DmaPktTxFifo_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaPktTxFifoSbeCnt_f},
    {DmaRegRdMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaRegRdMemSbeCnt_f},
    {DmaRegWrMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaRegWrMemSbeCnt_f},
    {DmaUserRegMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaUserRegMemSbeCnt_f},
    {DmaWrReqDataFifo_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaWrReqDataFifoSbeCnt_f},
    {DsAclVlanActionProfile_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsAclVlanActionProfileSbeCnt_f},
    {DsAging_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingSbeCnt_f},
    {DsAgingStatusFib_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingStatusFibSbeCnt_f},
    {DsAgingStatusTcam_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingStatusTcamSbeCnt_f},
    {DsBidiPimGroup_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsBidiPimGroupSbeCnt_f},
    {DsBufRetrvExcp_t,BufRetrvParityStatus_t,BufRetrvParityStatus_dsBufRetrvExcpSbeCnt_f},
    {DsCapwapFrag_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsCapwapFragSbeCnt_f},
    {DsCategoryIdPairHashLeftAd_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsCategoryIdPairHashLeftAdSbeCnt_f},
    {DsCategoryIdPairHashLeftKey_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsCategoryIdPairHashLeftKeySbeCnt_f},
    {DsCategoryIdPairHashRightAd_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsCategoryIdPairHashRightAdSbeCnt_f},
    {DsCategoryIdPairHashRightKey_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsCategoryIdPairHashRightKeySbeCnt_f},
    {DsCategoryIdPairTcamAd_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsCategoryIdPairTcamAdSbeCnt_f},
    {DsCFlexDstChannelBlockMask_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsCFlexDstChannelBlockMaskSbeCnt_f},
    {DsCFlexSrcPortBlockMask_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsCFlexSrcPortBlockMaskSbeCnt_f},
    {DsChannelizeIngFc_t,NetRxParityStatus_t,NetRxParityStatus_dsChannelizeIngFcSbeCnt_f},
    {DsChannelizeMode_t,NetRxParityStatus_t,NetRxParityStatus_dsChannelizeModeSbeCnt_f},
    {DsDestEthLmProfile_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_dsDestEthLmProfileSbeCnt_f},
    {DsDestInterface_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestInterfaceSbeCnt_f},
    {DsDestInterfaceProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestInterfaceProfileSbeCnt_f},
    {DsDestMapProfileMc_t,MetFifoParityStatus_t,MetFifoParityStatus_dsDestMapProfileMcSbeCnt_f},
    {DsDestMapProfileUc_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsDestMapProfileUcSbeCnt_f},
    {DsDestPort_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestPortSbeCnt_f},
    {DsDestPortChannelMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsDestPortChannelMapSbeCnt_f},
    {DsDestStpState_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestStpStateSbeCnt_f},
    {DsDestVlan_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanSbeCnt_f},
    {DsDestVlanProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanProfileSbeCnt_f},
    {DsDestVlanStatus_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanStatusSbeCnt_f},
    {DsDot1AeAesKey_t,MacSecEngineParityStatus_t,MacSecEngineParityStatus_dsDot1AeAesKeySbeCnt_f},
    {DsDot1AeSci_t,MacSecEngineParityStatus_t,MacSecEngineParityStatus_dsDot1AeSciSbeCnt_f},
    {DsEcmpGroup_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsEcmpGroupSbeCnt_f},
    {DsEcmpMember_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsEcmpMemberSbeCnt_f},
    {DsEcnMappingAction_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsEcnMappingActionSbeCnt_f},
    {DsEgressDiscardStats_t,EpeHdrEditParityStatus_t,EpeHdrEditParityStatus_dsEgressDiscardStatsSbeCnt_f},
    {DsEgressDot1AeSci_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsEgressDot1AeSciSbeCnt_f},
    {DsEgressDtls_t,CapwapProcParityStatus_t,CapwapProcParityStatus_dsEgressDtlsSbeCnt_f},
    {DsEgressIpfixConfig_t,FlowAccParityStatus_t,FlowAccParityStatus_dsEgressIpfixConfigSbeCnt_f},
    {DsEgressIpfixSamplingCount_t,FlowAccParityStatus_t,FlowAccParityStatus_dsEgressIpfixSamplingCountSbeCnt_f},
    {DsEgressPortMac_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsEgressPortMacSbeCnt_f},
    {DsEgressRouterMac_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsEgressRouterMacSbeCnt_f},
    {DsEgressVlanRangeProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsEgressVlanRangeProfileSbeCnt_f},
    {DsEgressVsi_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsEgressVsiSbeCnt_f},
    {DsElephantFlowState_t,EfdParityStatus_t,EfdParityStatus_dsElephantFlowStateSbeCnt_f},
    {DsEpePolicing0Config_t,PolicingEpeDebugStats_t,PolicingEpeDebugStats_dsEpePolicing0ConfigSbeCnt_f},
    {DsEpePolicing0CountX_t,PolicingEpeDebugStats_t,PolicingEpeDebugStats_dsEpePolicing0CountXSbeCnt_f},
    {DsEpePolicing0CountY_t,PolicingEpeDebugStats_t,PolicingEpeDebugStats_dsEpePolicing0CountYSbeCnt_f},
    {DsEpePolicing1Config_t,PolicingEpeDebugStats_t,PolicingEpeDebugStats_dsEpePolicing1ConfigSbeCnt_f},
    {DsEpePolicing1CountX_t,PolicingEpeDebugStats_t,PolicingEpeDebugStats_dsEpePolicing1CountXSbeCnt_f},
    {DsEpePolicing1CountY_t,PolicingEpeDebugStats_t,PolicingEpeDebugStats_dsEpePolicing1CountYSbeCnt_f},
    {DsErmAqmPortThrd_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmAqmPortThrdSbeCnt_f},
    {DsErmAqmQueueCfg_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmAqmQueueCfgSbeCnt_f},
    {DsErmAqmQueueStatus_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmAqmQueueStatusSbeCnt_f},
    {DsErmPortLimitedThrdProfile_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmPortLimitedThrdProfileSbeCnt_f},
    {DsErmQueueCfg_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmQueueCfgSbeCnt_f},
    {DsErmQueueLimitedThrdProfile_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmQueueLimitedThrdProfileSbeCnt_f},
    {DsErmResrcMonPortMax_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmResrcMonPortMaxSbeCnt_f},
    {DsGlbDestPort_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsGlbDestPortSbeCnt_f},
    {DsIngressIpfixConfig_t,FlowAccParityStatus_t,FlowAccParityStatus_dsIngressIpfixConfigSbeCnt_f},
    {DsIngressIpfixSamplingCount_t,FlowAccParityStatus_t,FlowAccParityStatus_dsIngressIpfixSamplingCountSbeCnt_f},
    {DsIpeCoPPConfig_t,CoppDebugStats_t,CoppDebugStats_dsIpeCoPPConfigSbeCnt_f},
    {DsIpeCoPPCountX_t,CoppDebugStats_t,CoppDebugStats_dsIpeCoPPCountXSbeCnt_f},
    {DsIpeCoPPCountY_t,CoppDebugStats_t,CoppDebugStats_dsIpeCoPPCountYSbeCnt_f},
    {DsIpePhbMutationCosMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePhbMutationCosMapSbeCnt_f},
    {DsIpePhbMutationDscpMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePhbMutationDscpMapSbeCnt_f},
    {DsIpePolicing0Config_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing0ConfigSbeCnt_f},
    {DsIpePolicing0CountX_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing0CountXSbeCnt_f},
    {DsIpePolicing0CountY_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing0CountYSbeCnt_f},
    {DsIpePolicing0ProfileX_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing0ProfileXSbeCnt_f},
    {DsIpePolicing0ProfileY_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing0ProfileYSbeCnt_f},
    {DsIpePolicing1Config_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing1ConfigSbeCnt_f},
    {DsIpePolicing1CountX_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing1CountXSbeCnt_f},
    {DsIpePolicing1CountY_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing1CountYSbeCnt_f},
    {DsIpePolicing1ProfileX_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing1ProfileXSbeCnt_f},
    {DsIpePolicing1ProfileY_t,PolicingIpeDebugStats_t,PolicingIpeDebugStats_dsIpePolicing1ProfileYSbeCnt_f},
    {DsIpePolicingPolicy_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePolicingPolicySbeCnt_f},
    {DsIpeStormCtl0Config_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl0ConfigSbeCnt_f},
    {DsIpeStormCtl0CountX_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl0CountXSbeCnt_f},
    {DsIpeStormCtl0CountY_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl0CountYSbeCnt_f},
    {DsIpeStormCtl0ProfileX_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl0ProfileXSbeCnt_f},
    {DsIpeStormCtl0ProfileY_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl0ProfileYSbeCnt_f},
    {DsIpeStormCtl1Config_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl1ConfigSbeCnt_f},
    {DsIpeStormCtl1CountX_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl1CountXSbeCnt_f},
    {DsIpeStormCtl1CountY_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl1CountYSbeCnt_f},
    {DsIpeStormCtl1ProfileX_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl1ProfileXSbeCnt_f},
    {DsIpeStormCtl1ProfileY_t,StormCtlDebugStats_t,StormCtlDebugStats_dsIpeStormCtl1ProfileYSbeCnt_f},
    {DsIpv6NatPrefix_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsIpv6NatPrefixSbeCnt_f},
    {DsIrmPortCnt_t,BufStoreParityStatus_t,BufStoreParityStatus_dsIrmPortCntSbeCnt_f},
    {DsIrmPortTcCnt_t,BufStoreParityStatus_t,BufStoreParityStatus_dsIrmPortTcCntSbeCnt_f},
    {DsL2Edit6WOuter_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsL2Edit6WOuterSbeCnt_f},
    {DsL3Edit6W3rd_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsL3Edit6W3rdSbeCnt_f},
    {DsLatencyMonCnt_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsLatencyMonCntSbeCnt_f},
    {DsLatencyWatermark_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsLatencyWatermarkSbeCnt_f},
    {DsLinkAggregateChannelMember_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateChannelMemberSbeCnt_f},
    {DsLinkAggregateMember_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateMemberSbeCnt_f},
    {DsLinkAggregateMemberSet_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateMemberSetSbeCnt_f},
    {DsLinkAggregationPortChannelMap_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregationPortChannelMapSbeCnt_f},
    {DsMacLimitCount_t,FibAccParityStatus_t,FibAccParityStatus_dsMacLimitCountSbeCnt_f},
    {DsMacLimitThreshold_t,FibAccParityStatus_t,FibAccParityStatus_dsMacLimitThresholdSbeCnt_f},
    {DsMetFifoExcp_t,MetFifoParityStatus_t,MetFifoParityStatus_dsMetFifoExcpSbeCnt_f},
    {DsMetLinkAggregateBitmap_t,MetFifoParityStatus_t,MetFifoParityStatus_dsMetLinkAggregateBitmapSbeCnt_f},
    {DsMetLinkAggregatePort_t,MetFifoParityStatus_t,MetFifoParityStatus_dsMetLinkAggregatePortSbeCnt_f},
    {DsMsgFreePtr_t,QMgrMsgStoreParityStatus_t,QMgrMsgStoreParityStatus_dsMsgFreePtrSbeCnt_f},
    {DsMsgUsedList_t,QMgrMsgStoreParityStatus_t,QMgrMsgStoreParityStatus_dsMsgUsedListSbeCnt_f},
    {DsPhyPort_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsPhyPortSbeCnt_f},
    {DsPhyPortExt_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsPhyPortExtSbeCnt_f},
    {DsPortBlockMask_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsPortBlockMaskSbeCnt_f},
    {DsPortIsolation_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsPortIsolationSbeCnt_f},
    {DsPortLinkAgg_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsPortLinkAggSbeCnt_f},
    {DsQcn_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsQcnSbeCnt_f},
    {DsQcnPortMac_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsQcnPortMacSbeCnt_f},
    {DsQMgrBaseSchMap_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrBaseSchMap1SbeCnt_f},
    {DsQMgrExtSchMap_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrExtSchMap1SbeCnt_f},
    {DsQueueMapTcamData_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsQueueMapTcamDataSbeCnt_f},
    {DsRouterMac_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsRouterMacSbeCnt_f},
    {DsRpf_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsRpfSbeCnt_f},
    {DsSrcChannel_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsSrcChannelSbeCnt_f},
    {DsSrcEthLmProfile_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsSrcEthLmProfileSbeCnt_f},
    {DsSrcInterface_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcInterfaceSbeCnt_f},
    {DsSrcInterfaceProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcInterfaceProfileSbeCnt_f},
    {DsSrcPort_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcPortSbeCnt_f},
    {DsSrcStpState_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcStpStateSbeCnt_f},
    {DsSrcVlan_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanSbeCnt_f},
    {DsSrcVlanProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanProfileSbeCnt_f},
    {DsSrcVlanStatus_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanStatusSbeCnt_f},
    {DsStats_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsSbeCnt_f},
    {DsStatsEgressACL0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressACL0SbeCnt_f},
    {DsStatsEgressGlobal0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal0SbeCnt_f},
    {DsStatsEgressGlobal1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal1SbeCnt_f},
    {DsStatsEgressGlobal2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal2SbeCnt_f},
    {DsStatsEgressGlobal3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal3SbeCnt_f},
    {DsStatsIngressACL0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL0SbeCnt_f},
    {DsStatsIngressACL1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL1SbeCnt_f},
    {DsStatsIngressACL2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL2SbeCnt_f},
    {DsStatsIngressACL3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL3SbeCnt_f},
    {DsStatsIngressGlobal0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal0SbeCnt_f},
    {DsStatsIngressGlobal1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal1SbeCnt_f},
    {DsStatsIngressGlobal2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal2SbeCnt_f},
    {DsStatsIngressGlobal3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal3SbeCnt_f},
    {DsStatsQueue_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsQueueSbeCnt_f},
    {DsVlan2Ptr_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsVlan2PtrSbeCnt_f},
    {DsVlanActionProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsVlanActionProfileSbeCnt_f},
    {DsVlanRangeProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsVlanRangeProfileSbeCnt_f},
    {DsVlanTagBitMap_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsVlanTagBitMapSbeCnt_f},
    {DsVlanXlateDefault_t,EgrOamHashParityStatus_t,EgrOamHashParityStatus_dsVlanXlateDefaultSbeCnt_f},
    {DsVrf_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsVrfSbeCnt_f},
    {DsVsi_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsVsiSbeCnt_f},
    {EpeClaEopInfoFifo_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_epeClaEopInfoFifoSbeCnt_f},
    {EpeClaPolicingSopInfoFifo_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_epeClaPolicingSopInfoRamSbeCnt_f},
    {EpeHdrAdjDataFifo_t,EpeHdrAdjParityStatus_t,EpeHdrAdjParityStatus_epeHdrAdjDataFifoSbeCnt_f},
    {EpeHdrAdjEopMsgFifo_t,EpeHdrAdjParityStatus_t,EpeHdrAdjParityStatus_epeHdrAdjEopMsgFifoSbeCnt_f},
    {EpeHdrEditPktCtlFifo_t,EpeHdrEditParityStatus_t,EpeHdrEditParityStatus_epeHdrEditPktCtlFifoSbeCnt_f},
    {IpeFwdExcepGroupMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_ipeFwdExcepGroupMapSbeCnt_f},
    {IpePhbDscpMap_t,IpePktProcParityStatus_t,IpePktProcParityStatus_ipePhbDscpMapSbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam10SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam9SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam8SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam7SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam6SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam5SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam4SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam3SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam2SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam1SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t,DynamicKeyParityStatus_shareKeyRam0SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd5SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd4SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd3SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd2SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd1SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd0SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam4SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam3SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam2SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam1SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam0SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam5SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam4SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam3SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam2SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam1SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam0SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamShareAd2SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamShareAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamShareAd0SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd7SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd6SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd5SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd4SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd3SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd2SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd0SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeUserIdAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeUserIdAd0SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamEpeAclAd2SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamEpeAclAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamEpeAclAd0SbeCnt_f},
     /*{McuSupDataMem0_t,McuSupStats0_t,McuSupStats0_mcuSupDataMemSbeCnt_f},*/
     /*{McuSupDataMem0_t,McuSupStats1_t,McuSupStats1_mcuSupDataMemSbeCnt_f},*/
    {McuSupProgMem1_t,McuSupStats0_t,McuSupStats0_mcuSupProgMemSbeCnt_f},
    {McuSupProgMem1_t,McuSupStats1_t,McuSupStats1_mcuSupProgMemSbeCnt_f},
    {MetBrRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metBrRcdFifoSbeCnt_f},
    {MetEnqRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metEnqRcdFifoSbeCnt_f},
    {MetMcastTrackFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metMcastTrackFifoSbeCnt_f},
    {MetMsgMem_t,MetFifoParityStatus_t,MetFifoParityStatus_metMsgMemSbeCnt_f},
    {MetRcdMem_t,MetFifoParityStatus_t,MetFifoParityStatus_metRcdMemSbeCnt_f},
    {MetUcastHiRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metUcastHiRcdFifoSbeCnt_f},
    {NetTxDsIbLppInfo_t,NetTxParityStatus_t,NetTxParityStatus_netTxDsIbLppInfoSbeCnt_f},
    {NetTxPktHdr0_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr0SbeCnt_f},
    {NetTxPktHdr1_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr1SbeCnt_f},
    {NetTxPktHdr2_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr2SbeCnt_f},
    {NetTxPktHdr3_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr3SbeCnt_f},
    {OamHashAclInputFifo_t,EgrOamHashParityStatus_t,EgrOamHashParityStatus_oamHashAclInputFifoSbeCnt_f},
    {OamHashLkupMgrInputFifo_t,EgrOamHashParityStatus_t,EgrOamHashParityStatus_oamHashLkupMgrInputFifoSbeCnt_f},
    {OamParserPktFifo_t,OamParserParityStatus_t,OamParserParityStatus_oamParserPktFifoSbeCnt_f},
    {MaxTblId_t, MaxTblId_t, 0}
};


uint16 drv_ecc_dt2_scan_tcam_tbl[][5] =
{
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Egr0_t,DsAclQosMacKey160Egr1_t,DsAclQosMacKey160Egr2_t,MaxTblId_t},
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Ing0_t,DsAclQosMacKey160Ing1_t,DsAclQosMacKey160Ing2_t,DsAclQosMacKey160Ing3_t},
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Ing4_t,DsAclQosMacKey160Ing5_t,DsAclQosMacKey160Ing6_t,DsAclQosMacKey160Ing7_t},
    {DRV_FTM_TCAM_KEY0,DsUserId0TcamKey160_t,DsUserId1TcamKey160_t,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_LPM_TCAM_KEY0,DsLpmTcamIpv4HalfKey_t,MaxTblId_t ,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_CID_TCAM,DsCategoryIdPairTcamKey_t,MaxTblId_t,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_QUEUE_TCAM,DsQueueMapTcamKey_t,MaxTblId_t,MaxTblId_t,MaxTblId_t},
    {MaxTblId_t,MaxTblId_t,MaxTblId_t,MaxTblId_t,MaxTblId_t}
};


#define DRV_MEM_REG(name, id, num, addr3w, addr6w, addr12w, E_SZ, ADD_SEL) \
    do{\
        drv_dt2_mem[id].entry_num = num;\
        drv_dt2_mem[id].addr_3w = addr3w;\
        drv_dt2_mem[id].addr_6w = addr6w;\
        drv_dt2_mem[id].addr_12w = addr12w;\
        drv_dt2_mem[id].entry_size = E_SZ<<2;\
        drv_dt2_mem[id].addr_sel = ADD_SEL;\
     }while(0)
#define DRV_MEM_REG_TCAM(name, id, SUB_ID, num, addr3w, addr6w, addr12w, TMID) \
    do{\
        drv_dt2_mem[id].entry_num = num;\
        drv_dt2_mem[id].addr_3w = addr3w;\
        drv_dt2_mem[id].addr_6w = addr6w;\
        drv_dt2_mem[id].addr_12w = addr12w;\
        drv_dt2_mem[id].tcam_map_id = TMID;\
        drv_dt2_mem[id].sub_id = SUB_ID;\
     }while(0)

drv_io_tcam_db_t drv_dt2_io_tcam_db[DRV_IO_TCAM_TYPE_NUM] = {
    {11,    DRV_BYTES_PER_ENTRY,        FlowTcamTcamMem_t,      FlowTcamTcamMem_tcamEntryValid_f, 8, DRV_FTM_TCAM_KEY0},
    {12,    DRV_LPM_KEY_BYTES_PER_ENTRY,LpmTcamTcamMem_t,       LpmTcamTcamMem_tcamEntryValid_f,  4, DRV_FTM_LPM_TCAM_KEY0},
    {12,    DRV_LPM_KEY_BYTES_PER_ENTRY,LpmTcamTcamMem_t,       LpmTcamTcamMem_tcamEntryValid_f,  4, DRV_FTM_LPM_TCAM_KEY8},
    {0,     0,                          0,                      0,                                0, 0},
    {0,     0,                          0,                      0,                                0, 0},
    {0,     0,                          0,                      0,                                0, 0},
    {0,     0,                          0,                      0,                                0, 0},
    {0,     0,                          0,                      0,                                0, 0},
    {0,     4,                          IpeCidTcamMem_t,        IpeCidTcamMem_tcamEntryValid_f,   2, DRV_FTM_CID_TCAM},
    {0,     8,                          QMgrEnqTcamMem_t,       QMgrEnqTcamMem_tcamEntryValid_f,  8, DRV_FTM_QUEUE_TCAM},
    {0,     0,                          0,                      0,                                0, 0},
    {0,     0,                          0,                      0,                                0, 0},
    {0,     0,                          0,                      0,                                0, 0}
};


/**
 @brief get flow tcam blknum and local index
*/
static  int32
drv_dt2_tcam_get_blknum_index(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32 *blknum, uint32 *local_idx)
{
    *local_idx = index;
    *blknum = TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0);

    return DRV_E_NONE;
}

static  int32
drv_flow_tcam_get_blknum_index(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32 *blknum, uint32 *local_idx)
{
    uint8 i;
    uint8 entry_num_each_idx = (TCAM_KEY_SIZE(lchip, tbl_id)/DRV_BYTES_PER_ENTRY);
    
    for (i = 0; i < TCAM_TABLE_BLK_NUM(lchip, tbl_id); i++)
    {
        if (index <= TCAM_TABLE_END(lchip, tbl_id, i)*entry_num_each_idx)
        {
            *blknum = TCAM_KEY_BLOCK_ID(lchip, tbl_id, i);
            *local_idx = index - TCAM_TABLE_START(lchip, tbl_id, i)*entry_num_each_idx;
            return DRV_E_NONE;
        }
    }

    return DRV_E_NONE;
}

int32
drv_mem_init_dt2(uint8 lchip)
{
    DRV_MEM_REG("KeyRam0"             , DRV_FTM_SRAM0,  16384, 0x6000000, 0x6800000, 0x7000000, 12, 2);
    DRV_MEM_REG("KeyRam1"             , DRV_FTM_SRAM1,  16384, 0x6080000, 0x6880000, 0x7080000, 12, 2);
    DRV_MEM_REG("KeyRam2"             , DRV_FTM_SRAM2,  16384, 0x6100000, 0x6900000, 0x7100000, 12, 2);
    DRV_MEM_REG("KeyRam3"             , DRV_FTM_SRAM3,  8192,  0x6180000, 0x6980000, 0x7180000, 12, 2);
    DRV_MEM_REG("KeyRam4"             , DRV_FTM_SRAM4,  8192,  0x6200000, 0x6a00000, 0x7200000, 12, 2);
    DRV_MEM_REG("KeyRam5"             , DRV_FTM_SRAM5,  8192,  0x6280000, 0x6a80000, 0x7280000, 12, 2);
    DRV_MEM_REG("KeyRam6"             , DRV_FTM_SRAM6,  8192,  0x6300000, 0x6b00000, 0x7300000, 12, 2);
    DRV_MEM_REG("KeyRam7"             , DRV_FTM_SRAM7,  8192,  0x6380000, 0x6b80000, 0x7380000, 12, 2);
    DRV_MEM_REG("KeyRam8"             , DRV_FTM_SRAM8,  4096,  0x6400000, 0x6c00000, 0x7400000, 12, 2);
    DRV_MEM_REG("KeyRam9"             , DRV_FTM_SRAM9,  4096,  0x6480000, 0x6c80000, 0x7480000, 12, 2);
    DRV_MEM_REG("KeyRam10"            , DRV_FTM_SRAM10, 2048,  0x6500000, 0x6d00000, 0x7500000, 12, 2);
    DRV_MEM_REG("AdRam0"              , DRV_FTM_SRAM11, 16384, 0x3800000, 0x3400000, 0x3000000, 12, 2);
    DRV_MEM_REG("AdRam1"              , DRV_FTM_SRAM12, 8192,  0x3880000, 0x3480000, 0x3080000, 12, 2);
    DRV_MEM_REG("AdRam2"              , DRV_FTM_SRAM13, 8192,  0x3900000, 0x3500000, 0x3100000, 12, 2);
    DRV_MEM_REG("AdRam3"              , DRV_FTM_SRAM14, 8192,  0x3980000, 0x3580000, 0x3180000, 12, 2);
    DRV_MEM_REG("AdRam4"              , DRV_FTM_SRAM15, 8192,  0x3a00000, 0x3600000, 0x3200000, 12, 2);
    DRV_MEM_REG("EditRam0"            , DRV_FTM_SRAM16, 8192,  0x1a00000, 0x1c00000, 0x1800000, 12, 2);
    DRV_MEM_REG("EditRam1"            , DRV_FTM_SRAM17, 8192,  0x1a40000, 0x1c40000, 0x1840000, 12, 2);
    DRV_MEM_REG("EditRam2"            , DRV_FTM_SRAM18, 8192,  0x1a80000, 0x1c80000, 0x1880000, 12, 2);
    DRV_MEM_REG("EditRam3"            , DRV_FTM_SRAM19, 8192,  0x1ac0000, 0x1cc0000, 0x18c0000, 12, 2);
    DRV_MEM_REG("EditRam4"            , DRV_FTM_SRAM20, 4096,  0x1b00000, 0x1d00000, 0x1900000, 12, 2);
    DRV_MEM_REG("EditRam5"            , DRV_FTM_SRAM21, 4096,  0x1b40000, 0x1d40000, 0x1940000, 12, 2);


    DRV_MEM_REG_TCAM("Tcam key0"           , DRV_FTM_TCAM_KEY0,  0, 1024, 0x1200000, 0xa0400000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key1"           , DRV_FTM_TCAM_KEY1,  1, 1024, 0x1210000, 0xa0408000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key2"           , DRV_FTM_TCAM_KEY2,  2, 1024, 0x1220000, 0xa0410000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key3"           , DRV_FTM_TCAM_KEY3,  3, 512,  0x1230000, 0xa0418000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key4"           , DRV_FTM_TCAM_KEY4,  4, 512,  0x1240000, 0xa0420000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key5"           , DRV_FTM_TCAM_KEY5,  5, 512,  0x1250000, 0xa0428000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key6"           , DRV_FTM_TCAM_KEY6,  6, 512,  0x1260000, 0xa0430000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key7"           , DRV_FTM_TCAM_KEY7,  7, 512,  0x1270000, 0xa0438000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key8"           , DRV_FTM_TCAM_KEY8,  8, 512,  0x1280000, 0xa0440000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key9"           , DRV_FTM_TCAM_KEY9,  9, 512,  0x1290000, 0xa0448000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key10"          , DRV_FTM_TCAM_KEY10, 10, 1024, 0x12a0000, 0xa0450000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key11"          , DRV_FTM_TCAM_KEY11, 11, 1024, 0x12b0000, 0xa0458000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key12"          , DRV_FTM_TCAM_KEY12, 12, 1024, 0x12c0000, 0xa0460000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key13"          , DRV_FTM_TCAM_KEY13, 13, 2048, 0x12d0000, 0xa0468000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key14"          , DRV_FTM_TCAM_KEY14, 14, 2048, 0x12e0000, 0xa0470000, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key15"          , DRV_FTM_TCAM_KEY15, 15, 2048, 0x12f0000, 0xa0478000, 0x0, 0);

    DRV_MEM_REG("Tcam AD0"            , DRV_FTM_TCAM_AD0,  1024, 0x1300000, 0x1300000, 0x1300000, 6, 0);
    DRV_MEM_REG("Tcam AD1"            , DRV_FTM_TCAM_AD1,  1024, 0x1308000, 0x1308000, 0x1308000, 6, 0);
    DRV_MEM_REG("Tcam AD2"            , DRV_FTM_TCAM_AD2,  1024, 0x1310000, 0x1310000, 0x1310000, 6, 0);
    DRV_MEM_REG("Tcam AD3"            , DRV_FTM_TCAM_AD3,  512,  0x1318000, 0x1318000, 0x1318000, 6, 0);
    DRV_MEM_REG("Tcam AD4"            , DRV_FTM_TCAM_AD4,  512,  0x1320000, 0x1320000, 0x1320000, 6, 0);
    DRV_MEM_REG("Tcam AD5"            , DRV_FTM_TCAM_AD5,  512,  0x1328000, 0x1328000, 0x1328000, 6, 0);
    DRV_MEM_REG("Tcam AD6"            , DRV_FTM_TCAM_AD6,  512,  0x1330000, 0x1330000, 0x1330000, 6, 0);
    DRV_MEM_REG("Tcam AD7"            , DRV_FTM_TCAM_AD7,  512,  0x1338000, 0x1338000, 0x1338000, 6, 0);
    DRV_MEM_REG("Tcam AD8"            , DRV_FTM_TCAM_AD8,  512,  0x1340000, 0x1340000, 0x1340000, 6, 0);
    DRV_MEM_REG("Tcam AD9"            , DRV_FTM_TCAM_AD9,  512,  0x1348000, 0x1348000, 0x1348000, 6, 0);
    DRV_MEM_REG("Tcam AD10"           , DRV_FTM_TCAM_AD10, 1024, 0x1350000, 0x1350000, 0x1350000, 6, 0);
    DRV_MEM_REG("Tcam AD11"           , DRV_FTM_TCAM_AD11, 1024, 0x1358000, 0x1358000, 0x1358000, 6, 0);
    DRV_MEM_REG("Tcam AD12"           , DRV_FTM_TCAM_AD12, 1024, 0x1360000, 0x1360000, 0x1360000, 6, 0);
    DRV_MEM_REG("Tcam AD13"           , DRV_FTM_TCAM_AD13, 2048, 0x1368000, 0x1368000, 0x1368000, 6, 0);
    DRV_MEM_REG("Tcam AD14"           , DRV_FTM_TCAM_AD14, 2048, 0x1370000, 0x1370000, 0x1370000, 6, 0);
    DRV_MEM_REG("Tcam AD15"           , DRV_FTM_TCAM_AD15, 2048, 0x1378000, 0x1378000, 0x1378000, 6, 0);

    DRV_MEM_REG_TCAM("LPM Tcam key0"       , DRV_FTM_LPM_TCAM_KEY0,  0, 512,  0x2100000, 0xa2800000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key1"       , DRV_FTM_LPM_TCAM_KEY1,  1, 512,  0x2102000, 0xa2801000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key2"       , DRV_FTM_LPM_TCAM_KEY2,  2, 512,  0x2104000, 0xa2802000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key3"       , DRV_FTM_LPM_TCAM_KEY3,  3, 512,  0x2106000, 0xa2803000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key4"       , DRV_FTM_LPM_TCAM_KEY4,  4, 512,  0x2110000, 0xa2808000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key5"       , DRV_FTM_LPM_TCAM_KEY5,  5, 512,  0x2112000, 0xa2809000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key6"       , DRV_FTM_LPM_TCAM_KEY6,  6, 512,  0x2114000, 0xa280a000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key7"       , DRV_FTM_LPM_TCAM_KEY7,  7, 512,  0x2116000, 0xa280b000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key8"       , DRV_FTM_LPM_TCAM_KEY8,  8, 1024, 0x2120000, 0xa2810000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key9"       , DRV_FTM_LPM_TCAM_KEY9,  9, 1024, 0x2124000, 0xa2812000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key10"      , DRV_FTM_LPM_TCAM_KEY10, 10, 1024, 0x2128000, 0xa2814000, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key11"      , DRV_FTM_LPM_TCAM_KEY11, 11, 1024, 0x212c000, 0xa2816000, 0x0, 1);

    DRV_MEM_REG("LPM Tcam Ad0"        , DRV_FTM_LPM_TCAM_AD0,  512,  0x2140000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad1"        , DRV_FTM_LPM_TCAM_AD1,  512,  0x2141000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad2"        , DRV_FTM_LPM_TCAM_AD2,  512,  0x2142000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad3"        , DRV_FTM_LPM_TCAM_AD3,  512,  0x2143000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad4"        , DRV_FTM_LPM_TCAM_AD4,  512,  0x2148000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad5"        , DRV_FTM_LPM_TCAM_AD5,  512,  0x2149000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad6"        , DRV_FTM_LPM_TCAM_AD6,  512,  0x214a000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad7"        , DRV_FTM_LPM_TCAM_AD7,  512,  0x214b000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad8"        , DRV_FTM_LPM_TCAM_AD8,  1024, 0x2150000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad9"        , DRV_FTM_LPM_TCAM_AD9,  1024, 0x2152000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad10"       , DRV_FTM_LPM_TCAM_AD10, 1024, 0x2154000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad11"       , DRV_FTM_LPM_TCAM_AD11, 1024, 0x2156000, 0x0, 0x0, 2, 0);

    DRV_MEM_REG_TCAM("Queue Tcam"         , DRV_FTM_QUEUE_TCAM, 0, 256, 0x00640000, 0xb1000000, 0x0, 3);
    DRV_MEM_REG_TCAM("Cid Tcam"           , DRV_FTM_CID_TCAM,   0, 128, 0x0093f400, 0xb0000000, 0x0, 2);

    return 0;
}





/*Diff between Tsingma and D2*/
int32
sys_duet2_ftm_get_edram_bitmap(uint8 lchip,
                                     uint8 sram_type,
                                     uint32* bit)
{
    switch (sram_type)
    {
        /* SelEdram  {edram0, edram3, edram6, edram7} Done */
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY0:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM3] = 1;
        bit[DRV_FTM_SRAM6] = 2;
        bit[DRV_FTM_SRAM7] = 3;
        break;

        /* SelEdram  {edram0, edram3, edram6, edram7} Done */
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY1:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM3] = 1;
        bit[DRV_FTM_SRAM6] = 2;
        bit[DRV_FTM_SRAM7] = 3;
        break;

        /* SelEdram  {edram0, edram1, edram2, edram3, edram4, edram5 } Done*/
        case DRV_FTM_SRAM_TBL_FIB0_HASH_KEY:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM1] = 1;
        bit[DRV_FTM_SRAM2] = 2;
        bit[DRV_FTM_SRAM3] = 3;
        bit[DRV_FTM_SRAM4] = 4;
        bit[DRV_FTM_SRAM5] = 5;
        break;

        /* SelEdram  {edram11, edram12, edram13, edram14, edram15} Done*/
    case DRV_FTM_SRAM_TBL_FLOW_AD:
        bit[DRV_FTM_SRAM11]   = 0;
        bit[DRV_FTM_SRAM12]   = 1;
        bit[DRV_FTM_SRAM13]   = 2;
        bit[DRV_FTM_SRAM14]   = 3;
        bit[DRV_FTM_SRAM15]   = 4;
        break;

        /* SelEdram  {edram0, edram5} Done*/
        case DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM5] = 1;
        break;

        /* SelEdram  {edram11, edram12} Done*/
    case DRV_FTM_SRAM_TBL_IPFIX_AD:
        bit[DRV_FTM_SRAM11] = 0;
        bit[DRV_FTM_SRAM12] = 1;
        break;

        /* SelEdram  {edram11, edram12, edram13, edram14, edram15} Done*/
        case DRV_FTM_SRAM_TBL_DSMAC_AD:
        bit[DRV_FTM_SRAM11]   = 0;
        bit[DRV_FTM_SRAM12]   = 1;
        bit[DRV_FTM_SRAM13]   = 2;
        bit[DRV_FTM_SRAM14]   = 3;
        bit[DRV_FTM_SRAM15]   = 4;
        break;

        /* SelEdram  {edram11, edram12, edram13, edram14, edram15} Done*/
        case DRV_FTM_SRAM_TBL_DSIP_AD:
        bit[DRV_FTM_SRAM11]   = 0;
        bit[DRV_FTM_SRAM12]   = 1;
        bit[DRV_FTM_SRAM13]   = 2;
        bit[DRV_FTM_SRAM14]   = 3;
        bit[DRV_FTM_SRAM15]   = 4;
        break;

        /* SelEdram  {edram18, edram19, edram20, edram21 } Done*/
    case DRV_FTM_SRAM_TBL_EDIT:
        bit[DRV_FTM_SRAM18] = 0;
        bit[DRV_FTM_SRAM19] = 1;
        bit[DRV_FTM_SRAM20] = 2;
        bit[DRV_FTM_SRAM21] = 3;
        break;

        /* SelEdram  {edram16, edram18, edram19, edram20, edram21 } Done*/
        case DRV_FTM_SRAM_TBL_NEXTHOP:
        bit[DRV_FTM_SRAM16] = 0;
        bit[DRV_FTM_SRAM18] = 1;
        bit[DRV_FTM_SRAM19] = 2;
        bit[DRV_FTM_SRAM20] = 3;
        bit[DRV_FTM_SRAM21] = 4;
        break;

        /* SelEdram  {edram16, edram18, edram19, edram20, edram21 } Done*/
        case DRV_FTM_SRAM_TBL_MET:
        bit[DRV_FTM_SRAM16] = 0;
        bit[DRV_FTM_SRAM18] = 1;
        bit[DRV_FTM_SRAM19] = 2;
        bit[DRV_FTM_SRAM20] = 3;
        bit[DRV_FTM_SRAM21] = 4;
        break;

        /* SelEdram  {edram17, edram18, edram19, edram20, edram21 } Done*/
        case DRV_FTM_SRAM_TBL_FWD:
        bit[DRV_FTM_SRAM17] = 0;
        bit[DRV_FTM_SRAM18] = 1;
        bit[DRV_FTM_SRAM19] = 2;
        bit[DRV_FTM_SRAM20] = 3;
        bit[DRV_FTM_SRAM21] = 4;
        break;


        /* SelEdram  {edram11, edram12, edram13, edram14, edram15} Done*/
        case DRV_FTM_SRAM_TBL_USERID_AD:
        bit[DRV_FTM_SRAM11]   = 0;
        bit[DRV_FTM_SRAM12]   = 1;
        bit[DRV_FTM_SRAM13]   = 2;
        bit[DRV_FTM_SRAM14]   = 3;
        bit[DRV_FTM_SRAM15]   = 4;
        break;

         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_LM:
        bit[DRV_FTM_SRAM1] = 0;
        bit[DRV_FTM_SRAM4] = 1;
        break;

         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_MEP:
        bit[DRV_FTM_SRAM1] = 0;
        bit[DRV_FTM_SRAM4] = 1;
        break;

         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_MA:
        bit[DRV_FTM_SRAM1] = 0;
        bit[DRV_FTM_SRAM4] = 1;
        break;

         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_MA_NAME:
        bit[DRV_FTM_SRAM1] = 0;
        bit[DRV_FTM_SRAM4] = 1;
        break;


        /* NONE */
        case DRV_FTM_SRAM_TBL_FIB1_HASH_KEY:
        bit[DRV_FTM_SRAM6] = 0;
        bit[DRV_FTM_SRAM7] = 1;
        bit[DRV_FTM_SRAM8] = 2;
        bit[DRV_FTM_SRAM9] = 3;
        bit[DRV_FTM_SRAM10] = 4;
        break;

        /* NONE */
    case DRV_FTM_SRAM_TBL_FLOW_HASH_KEY:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM1] = 1;
        bit[DRV_FTM_SRAM2] = 2;
        bit[DRV_FTM_SRAM3] = 3;
        bit[DRV_FTM_SRAM4] = 4;
        break;

         /* NONE */
        case DRV_FTM_SRAM_TBL_OAM_APS:
        bit[DRV_FTM_SRAM10] = 0;
        break;

        /* NONE */
        case DRV_FTM_SRAM_TBL_XCOAM_HASH_KEY:
        bit[DRV_FTM_SRAM2] = 0;
        bit[DRV_FTM_SRAM5] = 1;
        break;

        /* NONE */
        case DRV_FTM_SRAM_TBL_USERID_HASH_KEY:
        bit[DRV_FTM_SRAM6] = 0;
        bit[DRV_FTM_SRAM7] = 1;
        bit[DRV_FTM_SRAM8] = 2;
        bit[DRV_FTM_SRAM9] = 3;
        bit[DRV_FTM_SRAM10] = 4;
        break;

        default:
           break;
    }

    return DRV_E_NONE;
}

int32 drv_duet2_get_mcu_lock_id(uint8 lchip, tbls_id_t tbl_id, uint8* p_mcu_id, uint32* p_lock_id)
{
    uint8  mcu_id  = 0xff;
    uint32 lock_id = DRV_MCU_LOCK_NONE;

    if((NULL == p_lock_id) || (NULL == p_mcu_id))
    {
        return DRV_E_INVALID_PTR;
    }

    if ((NetTxWriteEn_t == tbl_id)
        || ((tbl_id >= Sgmac0TxCfg0_t) && (tbl_id <= Sgmac0TxCfg15_t))
        || ((tbl_id >= Sgmac1TxCfg0_t) && (tbl_id <= Sgmac1TxCfg15_t))
        || ((tbl_id >= Sgmac2TxCfg0_t) && (tbl_id <= Sgmac2TxCfg15_t))
        || ((tbl_id >= Sgmac3TxCfg0_t) && (tbl_id <= Sgmac3TxCfg15_t))
        || ((tbl_id >= SharedMii0Cfg0_t) && (tbl_id <= SharedMii0Cfg15_t))
        || ((tbl_id >= SharedMii1Cfg0_t) && (tbl_id <= SharedMii1Cfg15_t))
        || ((tbl_id >= SharedMii2Cfg0_t) && (tbl_id <= SharedMii2Cfg15_t))
        || ((tbl_id >= SharedMii3Cfg0_t) && (tbl_id <= SharedMii3Cfg15_t)))
    {
        lock_id = DRV_MCU_LOCK_WA_CFG;
        mcu_id  = 0;
    }

    *p_mcu_id  = mcu_id;
    *p_lock_id = lock_id;

    return DRV_E_NONE;
}

int32 drv_duet2_get_mcu_addr(uint8 mcu_id, uint32* mutex_data_addr, uint32* mutex_mask_addr)
{
    if((NULL == mutex_data_addr) || (NULL == mutex_mask_addr))
    {
        return DRV_E_INVALID_PTR;
    }
    if(0 != mcu_id)
    {
        return DRV_E_EXCEED_MAX_SIZE;
    }
    *mutex_data_addr = MCU0_MUTEX0_CPU_DATA;
    *mutex_mask_addr = MCU0_MUTEX0_CPU_MASK;
    return DRV_E_NONE;
}

int32
drv_duet2_chip_read_hss15g(uint8 lchip, uint8 hssid, uint32 addr, uint16* p_data)
{
    int32 ret = 0;
    HsMacroPrtReq0_m hss_req;
    HsMacroPrtAck0_m hss_ack;
    uint32 cmd = 0;
    uint32 timeout = DRV_CMD_TIMEOUT;
    HsMacroPrtReqId0_m req_id;

    DRV_PTR_VALID_CHECK(p_data);
    DRV_INIT_CHECK(lchip);

    if (hssid > DRV_HSS15G_MACRO_NUM - 1)
    {
        return DRV_E_EXCEED_MAX_SIZE;
    }

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    sal_memset(&hss_req, 0, sizeof(HsMacroPrtReq0_m));
    sal_memset(&hss_ack, 0, sizeof(HsMacroPrtAck0_m));
    sal_memset(&req_id, 0, sizeof(HsMacroPrtReqId0_m));

    /* 1. write reqId to hss15g access */
    SetHsMacroPrtReqId0(V, reqId_f, &req_id, 16);
    cmd = DRV_IOW((HsMacroPrtReqId0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &req_id);

    cmd = DRV_IOR((HsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);
    if (GetHsMacroPrtReq0(V, reqPrtValid_f, &hss_req))
    {
        return DRV_E_OCCPANCY;
    }

    /* 2. Write request address, Trigger read commend */
    SetHsMacroPrtReq0(V, reqPrtAddr_f, &hss_req, addr);
    SetHsMacroPrtReq0(V, reqPrtIsRead_f , &hss_req, 1);
    SetHsMacroPrtReq0(V, reqPrtValid_f , &hss_req, 1);
    cmd = DRV_IOW((HsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }


    if (0 == SDK_WORK_PLATFORM)
    {
        /* 3. Read hssReadDataValid register, and check whether current accssing is done */
        cmd = DRV_IOR((HsMacroPrtAck0_t+hssid), DRV_ENTRY_FLAG);
        ret = DRV_IOCTL(lchip, 0, cmd, &hss_ack);
        if (ret < 0)
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }

        while (!GetHsMacroPrtAck0(V, ackPrtValid_f, &hss_ack) && (--timeout))
        {
            if (GetHsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
            {
                break;
            }
        }

        if (!GetHsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
    }

    /* 4. Read hssReadData registers */
    *p_data = GetHsMacroPrtAck0(V, ackPrtReadData_f, &hss_ack);

    return DRV_E_NONE;
}

/**
 @brief access hss15g control register
*/
int32
drv_duet2_chip_write_hss15g(uint8 lchip, uint8 hssid, uint32 addr, uint16 data)
{
    int32 ret = 0;
    HsMacroPrtReq0_m hss_req;
    HsMacroPrtAck0_m hss_ack;
    HsMacroPrtReqId0_m req_id;
    uint32 cmd = 0;
    uint32 timeout = DRV_CMD_TIMEOUT;
    uint32 tmp_val32 = 0;

    DRV_INIT_CHECK(lchip);

    if (hssid > DRV_HSS15G_MACRO_NUM - 1)
    {
        return DRV_E_EXCEED_MAX_SIZE;
    }

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    sal_memset(&hss_req, 0, sizeof(HsMacroPrtReq0_m));
    sal_memset(&hss_ack, 0, sizeof(HsMacroPrtAck0_m));
    sal_memset(&req_id, 0, sizeof(HsMacroPrtReqId0_m));

    /* 1. write reqId to hss15g access */
    tmp_val32 = 16;
    DRV_IOW_FIELD(lchip, (HsMacroPrtReqId0_t+hssid), HsMacroPrtReqId0_reqId_f, &tmp_val32, &req_id);

    cmd = DRV_IOW((HsMacroPrtReqId0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &req_id);

    cmd = DRV_IOR((HsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);
    if (GetHsMacroPrtReq0(V, reqPrtValid_f, &hss_req))
    {
        return DRV_E_OCCPANCY;
    }

    /* 2. Write request addr and data, trigger write operation*/
    tmp_val32 = (uint32)addr;
    DRV_IOW_FIELD(lchip, (HsMacroPrtReq0_t+hssid), HsMacroPrtReq0_reqPrtAddr_f, &tmp_val32, &hss_req);
    tmp_val32 = (uint32)data;
    DRV_IOW_FIELD(lchip, (HsMacroPrtReq0_t+hssid), HsMacroPrtReq0_reqPrtWriteData_f, &tmp_val32, &hss_req);
    tmp_val32 = 0;
    DRV_IOW_FIELD(lchip, (HsMacroPrtReq0_t+hssid), HsMacroPrtReq0_reqPrtIsRead_f, &tmp_val32, &hss_req);
    tmp_val32 = 1;
    DRV_IOW_FIELD(lchip, (HsMacroPrtReq0_t+hssid), HsMacroPrtReq0_reqPrtValid_f, &tmp_val32, &hss_req);
    cmd = DRV_IOW((HsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    if (0 == SDK_WORK_PLATFORM)
    {
        /* 3. Read hssReadDataValid register, and check whether current accssing is done */
        cmd = DRV_IOR((HsMacroPrtAck0_t+hssid), DRV_ENTRY_FLAG);
        ret = DRV_IOCTL(lchip, 0, cmd, &hss_ack);
        if (ret < 0)
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
        while (!GetHsMacroPrtAck0(V, ackPrtValid_f, &hss_ack) && (--timeout))
        {
            if (GetHsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
            {
                break;
            }
        }

        if (!GetHsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
    }

    return DRV_E_NONE;
}

/**
 @brief access hss28g control register
*/
int32
drv_duet2_chip_read_hss28g(uint8 lchip, uint8 hssid, uint32 addr, uint16* p_data)
{
    int32 ret = 0;
    CsMacroPrtReq0_m hss_req;
    CsMacroPrtAck0_m hss_ack;
    CsMacroPrtReqId0_m req_id;
    uint32 cmd = 0;
    uint32 timeout = DRV_CMD_TIMEOUT;

    DRV_PTR_VALID_CHECK(p_data);
    DRV_INIT_CHECK(lchip);

    if (hssid > DRV_HSS28G_MACRO_NUM - 1)
    {
        return DRV_E_EXCEED_MAX_SIZE;
    }

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    sal_memset(&hss_req, 0, sizeof(CsMacroPrtReq0_m));
    sal_memset(&hss_ack, 0, sizeof(CsMacroPrtAck0_m));
    sal_memset(&req_id, 0, sizeof(CsMacroPrtReqId0_m));

    /* 1. write reqId to hss28g access */
    SetCsMacroPrtReqId0(V, reqId_f, &req_id, 8);
    cmd = DRV_IOW((CsMacroPrtReqId0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &req_id);

    cmd = DRV_IOR((CsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);
    if (GetCsMacroPrtReq0(V, reqPrtValid_f, &hss_req))
    {
        return DRV_E_OCCPANCY;
    }

    /* 2. Write request address, Trigger read commend */
    SetCsMacroPrtReq0(V, reqPrtAddr_f, &hss_req, addr);
    SetCsMacroPrtReq0(V, reqPrtIsRead_f , &hss_req, 1);
    SetCsMacroPrtReq0(V, reqPrtValid_f , &hss_req, 1);
    cmd = DRV_IOW((CsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    if (0 == SDK_WORK_PLATFORM)
    {
        /* 3. Read hssReadDataValid register, and check whether current accssing is done */
        cmd = DRV_IOR((CsMacroPrtAck0_t+hssid), DRV_ENTRY_FLAG);
        ret = DRV_IOCTL(lchip, 0, cmd, &hss_ack);
        if (ret < 0)
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }

        while (!GetCsMacroPrtAck0(V, ackPrtValid_f, &hss_ack) && (--timeout))
        {
            if (GetCsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
            {
                break;
            }
        }

        if (!GetCsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
    }

    /* 4. Read hssReadData registers */
    *p_data = GetCsMacroPrtAck0(V, ackPrtReadData_f, &hss_ack);

    return DRV_E_NONE;
}

/**
 @brief access hss28g control register
*/
int32
drv_duet2_chip_write_hss28g(uint8 lchip, uint8 hssid, uint32 addr, uint16 data)
{
    int32 ret = 0;
    CsMacroPrtReq0_m hss_req;
    CsMacroPrtAck0_m hss_ack;
    CsMacroPrtReqId0_m req_id;
    uint32 cmd = 0;
    uint32 timeout = DRV_CMD_TIMEOUT;
    uint32 tmp_val32 = 0;

    DRV_INIT_CHECK(lchip);

    if (hssid > DRV_HSS28G_MACRO_NUM - 1)
    {
        return DRV_E_EXCEED_MAX_SIZE;
    }

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    sal_memset(&hss_req, 0, sizeof(CsMacroPrtReq0_m));
    sal_memset(&hss_ack, 0, sizeof(CsMacroPrtAck0_m));
    sal_memset(&req_id, 0, sizeof(CsMacroPrtReqId0_m));

    /* 1. write reqId to hss28g access */
    tmp_val32 = 8;
    DRV_IOW_FIELD(lchip, (CsMacroPrtReqId0_t+hssid), CsMacroPrtReqId0_reqId_f, &tmp_val32, &req_id);
    cmd = DRV_IOW((CsMacroPrtReqId0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &req_id);

    cmd = DRV_IOR((CsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);

    if (GetCsMacroPrtReq0(V, reqPrtValid_f, &hss_req))
    {
        return DRV_E_OCCPANCY;
    }

    /* 2. Write request addr and data */
    tmp_val32 = (uint32)addr;
    DRV_IOW_FIELD(lchip, (CsMacroPrtReq0_t+hssid), CsMacroPrtReq0_reqPrtAddr_f, &tmp_val32, &hss_req);
    tmp_val32 = (uint32)data;
    DRV_IOW_FIELD(lchip, (CsMacroPrtReq0_t+hssid), CsMacroPrtReq0_reqPrtWriteData_f, &tmp_val32, &hss_req);
    tmp_val32 = 0;
    DRV_IOW_FIELD(lchip, (CsMacroPrtReq0_t+hssid), CsMacroPrtReq0_reqPrtIsRead_f, &tmp_val32, &hss_req);
    tmp_val32 = 1;
    DRV_IOW_FIELD(lchip, (CsMacroPrtReq0_t+hssid), CsMacroPrtReq0_reqPrtValid_f, &tmp_val32, &hss_req);
    cmd = DRV_IOW((CsMacroPrtReq0_t+hssid), DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &hss_req);

    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    if (0 == SDK_WORK_PLATFORM)
    {
        /* 3. Read hssReadDataValid register, and check whether current accssing is done */
        cmd = DRV_IOR((CsMacroPrtAck0_t+hssid), DRV_ENTRY_FLAG);
        ret = DRV_IOCTL(lchip, 0, cmd, &hss_ack);
        if (ret < 0)
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }

        while (!GetCsMacroPrtAck0(V, ackPrtValid_f, &hss_ack) && (--timeout))
        {
            if (GetCsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
            {
                break;
            }
        }

        if (!GetCsMacroPrtAck0(V, ackPrtValid_f, &hss_ack))
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
    }

    return DRV_E_NONE;
}

int32
drv_enum_init_duet2(uint8 lchip)
{
    DRV_CONST(DRV_IPFIX_EXPORTREASON_NO_EXPORT)                  = 0x0;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_EXPIRED)                    = 0x1;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_TCP_SESSION_CLOSE)          = 0x2;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_PACKET_COUNT_OVERFLOW)      = 0x3;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_BYTE_COUNT_OVERFLOW)        = 0x4;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_NEW_FLOW_EXPORT)            = 0x5;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_DESTINATION_CHANGE)         = 0x6;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_TS_COUNT_OVERFLOW)          = 0x7;

    DRV_CONST(DRV_DS_CATEGORY_ID_PAIR_TCAM_LOOKUP_KEY_BYTES) = 4;
    DRV_CONST(DRV_TCAMKEYTYPE_MACKEY_160)               = 0x0;
    DRV_CONST(DRV_TCAMKEYTYPE_L3KEY_160)                = 0x1;
    DRV_CONST(DRV_TCAMKEYTYPE_L3KEY_320)                = 0x2;
    DRV_CONST(DRV_TCAMKEYTYPE_IPV6KEY_320)              = 0x3;
    DRV_CONST(DRV_TCAMKEYTYPE_IPV6KEY_640)              = 0x4;
    DRV_CONST(DRV_TCAMKEYTYPE_MACL3KEY_320)             = 0x5;
    DRV_CONST(DRV_TCAMKEYTYPE_MACL3KEY_640)             = 0x6;
    DRV_CONST(DRV_TCAMKEYTYPE_MACIPV6KEY_640)           = 0x7;
    DRV_CONST(DRV_TCAMKEYTYPE_CIDKEY_160)               = 0x8;
    DRV_CONST(DRV_TCAMKEYTYPE_SHORTKEY_80)              = 0x9;
    DRV_CONST(DRV_TCAMKEYTYPE_FORWARDKEY_320)           = 0xa;
    DRV_CONST(DRV_TCAMKEYTYPE_FORWARDKEY_640)           = 0xb;
    DRV_CONST(DRV_TCAMKEYTYPE_COPPKEY_320)              = 0xc;
    DRV_CONST(DRV_TCAMKEYTYPE_COPPKEY_640)              = 0xd;
    DRV_CONST(DRV_TCAMKEYTYPE_UDFKEY_320)               = 0xe;
    DRV_CONST(DRV_XC_OAM_HASH_CAM_NUM)      = 128;

    /*DRV_CONST(DRV_SCL_KEY_TYPE_L2KEY);*/
    /*DRV_CONST(DRV_SCL_KEY_TYPE_L3KEY) ;*/
    /*DRV_CONST(DRV_SCL_KEY_TYPE_L2L3KEY) ;*/
    DRV_CONST(DRV_SCL_KEY_TYPE_MACKEY160)               = 0x0;
    DRV_CONST(DRV_SCL_KEY_TYPE_MACL3KEY320)             = 0x2;
    DRV_CONST(DRV_SCL_KEY_TYPE_L3KEY160)                = 0x1;
    DRV_CONST(DRV_SCL_KEY_TYPE_IPV6KEY320)              = 0x1;
    DRV_CONST(DRV_SCL_KEY_TYPE_MACIPV6KEY640)           = 0x2;
    DRV_CONST(DRV_SCL_KEY_TYPE_RESOLVE_CONFLICT)        = 0x3;
    DRV_CONST(DRV_SCL_KEY_TYPE_UDFKEY160)               = 0x6;
    DRV_CONST(DRV_SCL_KEY_TYPE_UDFKEY320)               = 0x4;

    DRV_CONST(DRV_SCL_KEY_TYPE_MASK)                    = 0x3;

    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L2)                = 0x0;
    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L3)                = 0x1;
    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L4)                = 0x2;
    DRV_CONST(DRV_UDFPOSTYPE_NONE)                    = 0x3;
   /* DRV_CONST(DRV_UDFPOSTYPE_INNER_L2); */
   /* DRV_CONST(DRV_UDFPOSTYPE_INNER_L3); */
   /* DRV_CONST(DRV_UDFPOSTYPE_INNER_L4); */
   /* DRV_CONST(DRV_UDFPOSTYPE_RSV); */
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_DISABLE )             = 0x0;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_DOUBLEVLANPORT)       = 0x1;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANPORT)            = 0x2;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_CVLANPORT)            = 0x3;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANCOSPORT)         = 0x4;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_CVLANCOSPORT)         = 0x5;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORTVLANCROSS)        = 0x6;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORTCROSS)            = 0x7;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORT)                 = 0x8;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANPORTMAC)         = 0x9;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_TUNNELPBB)            = 0xa;

    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_ETH)                  = 0x10;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_BFD)                  = 0x11;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_MPLSLABEL)            = 0x12;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_MPLSSECTION)          = 0x13;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_RMEP)                 = 0x14;

    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_FCOE)             = 0x0;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV4)             = 0x1;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6MCAST)        = 0x2;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6UCAST)        = 0x3;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MAC)              = 0x4;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MACIPV6MCAST)     = 0x5;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_TRILL)            = 0x6;


    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV4)             = 0x0;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV6NATDA)        = 0x1;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV6NATSA)        = 0x2;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_OTHER)            = 0x3;

    DRV_CONST(DRV_FLOWHASHTYPE_INVALID)                     = 0x0;
    DRV_CONST(DRV_FLOWHASHTYPE_L2)                          = 0x1;
    DRV_CONST(DRV_FLOWHASHTYPE_L2L3)                        = 0x2;
    DRV_CONST(DRV_FLOWHASHTYPE_L3IPV4)                      = 0x3;
    DRV_CONST(DRV_FLOWHASHTYPE_L3IPV6)                      = 0x4;
    DRV_CONST(DRV_FLOWHASHTYPE_L3MPLS)                      = 0x5;

    DRV_CONST(DRV_USERIDHASHTYPE_DISABLE)                   = 0x0;
    DRV_CONST(DRV_USERIDHASHTYPE_DOUBLEVLANPORT)            = 0x1;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANPORT)                 = 0x2;
    DRV_CONST(DRV_USERIDHASHTYPE_CVLANPORT)                 = 0x3;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANCOSPORT)              = 0x4;
    DRV_CONST(DRV_USERIDHASHTYPE_CVLANCOSPORT)              = 0x5;
    DRV_CONST(DRV_USERIDHASHTYPE_MACPORT)                   = 0x6;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV4PORT)                  = 0x7;
    DRV_CONST(DRV_USERIDHASHTYPE_MAC)                       = 0x8;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV4SA)                    = 0x9;
    DRV_CONST(DRV_USERIDHASHTYPE_PORT)                      = 0xa;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANMACSA)                = 0xb;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLAN)                     = 0xc;
    DRV_CONST(DRV_USERIDHASHTYPE_ECIDNAMESPACE)             = 0xd;
    DRV_CONST(DRV_USERIDHASHTYPE_INGECIDNAMESPACE)          = 0xe;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV6SA)                    = 0xf;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV6PORT)                  = 0x10;



    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPSTASTATUS)           = 0x11;
    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPSTASTATUSMC)         = 0x12;
    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPMACDAFORWARD)        = 0x13;
    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPVLANFORWARD)         = 0x14;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4)                = 0x15;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTYPE_START)         = DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4);
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4GREKEY)          = 0x16;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UDP)             = 0x17;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELPBB)                 = 0x18;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLUCRPF)          = 0x19;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLUCDECAP)        = 0x1a;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCRPF)          = 0x1b;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCDECAP)        = 0x1c;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCADJ)          = 0x1d;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4RPF)             = 0x1e;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCVXLANMODE0)    = 0x1f;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCVXLANMODE1)    = 0x20;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCVXLANMODE0)    = 0x21;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCVXLANMODE1)    = 0x22;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCNVGREMODE0)    = 0x23;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCNVGREMODE1)    = 0x24;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCNVGREMODE0)    = 0x25;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCNVGREMODE1)    = 0x26;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4MCVXLANMODE0)    = 0x27;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4VXLANMODE1)      = 0x28;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCVXLANMODE0)    = 0x29;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCVXLANMODE1)    = 0x2a;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4MCNVGREMODE0)    = 0x2b;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4NVGREMODE1)      = 0x2c;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCNVGREMODE0)    = 0x2d;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCNVGREMODE1)    = 0x2e;


    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4CAPWAP)          = 0x2f;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6CAPWAP)          = 0x30;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELCAPWAPRMAC)          = 0x31;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELCAPWAPRMACRID)       = 0x32;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELMPLS)                = 0x34;


    #if 0
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6)                = 0x33;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6GREKEY)          = 0x34;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UDP)             = 0x35;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6DA)              = 0x36;
    #endif
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4DA)              = 0x33;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTYPE_END)        = DRV_CONST(DRV_USERIDHASHTYPE_TUNNELMPLS);
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL2)                 = 0x35;
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWTYPE_END)        = DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL2);


    DRV_CONST(DRV_USERIDPORTHASHTYPE_DISABLE)              = 0x0;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_DOUBLEVLANPORT)       = 0x1;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANPORT)            = 0x2;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_CVLANPORT)            = 0x3;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANCOSPORT)         = 0x4;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_CVLANCOSPORT)         = 0x5;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_MACPORT)              = 0x6;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_IPSAPORT)             = 0x7;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_MAC)                  = 0x8;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_IPSA)                 = 0x9;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_PORT)                 = 0xa;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANMACSA)           = 0xb;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLAN)                = 0xc;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_ECIDNAMESPACE)        = 0xd;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_INGECIDNAMESPACE)     = 0xe;

    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANDSCPPORT)        = 0xf;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SCLTYPE_END)         = DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANDSCPPORT);
    DRV_CONST(DRV_USERIDPORTHASHTYPE_TUNNEL)               = 0x1d;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SCLFLOW)              = 0x1e;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_TRILL)                = 0x1f;



    DRV_CONST(DRV_STK_MUX_TYPE_HDR_REGULAR_PORT)      = 0x0;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITHOUT_TUNNEL)    = 0x6;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2)           = 0x7;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2_AND_IPV4)  = 0x8;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2_AND_IPV6)  = 0x9;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_IPV4)         = 0xa;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_IPV6)         = 0xb;

    DRV_CONST(DRV_DMA_PACKET_TX_CHAN_NUM) = 2;
    DRV_CONST(DRV_DMA_PACKET_RX_CHAN_NUM) = 4;
    DRV_CONST(DRV_DMA_PACKET_RX0_CHAN_ID) = 0;
    DRV_CONST(DRV_DMA_PACKET_RX1_CHAN_ID) = 1;
    DRV_CONST(DRV_DMA_PACKET_RX2_CHAN_ID) = 2;
    DRV_CONST(DRV_DMA_PACKET_RX3_CHAN_ID) = 3;
    DRV_CONST(DRV_DMA_PACKET_TX0_CHAN_ID) = 4;
    DRV_CONST(DRV_DMA_PACKET_TX1_CHAN_ID) = 5;
    DRV_CONST(DRV_DMA_TBL_WR_CHAN_ID)     = 6;
    DRV_CONST(DRV_DMA_TBL_RD_CHAN_ID)     = 7;
    DRV_CONST(DRV_DMA_PORT_STATS_CHAN_ID) = 8;
    DRV_CONST(DRV_DMA_FLOW_STATS_CHAN_ID) = 9;
    DRV_CONST(DRV_DMA_BUF_SCAN_CHAN_ID)   = 0xFF;
    DRV_CONST(DRV_DMA_REG_MAX_CHAN_ID)    = 10;
    DRV_CONST(DRV_DMA_LEARNING_CHAN_ID)   = 11;
    DRV_CONST(DRV_DMA_HASHKEY_CHAN_ID)    = 12;
    DRV_CONST(DRV_DMA_IPFIX_CHAN_ID)      = 13;
    DRV_CONST(DRV_DMA_SDC_CHAN_ID)        = 14;
    DRV_CONST(DRV_DMA_MONITOR_CHAN_ID)    = 15;
    DRV_CONST(DRV_DMA_PKT_TX_TIMER_CHAN_ID) = 5;

    DRV_CONST(DRV_DMA_PACKET_TX2_CHAN_ID) = 30;
    DRV_CONST(DRV_DMA_PACKET_TX3_CHAN_ID) = 30;
    DRV_CONST(DRV_DMA_TBL_RD1_CHAN_ID) = 30;
    DRV_CONST(DRV_DMA_TBL_RD2_CHAN_ID) = 30;
    DRV_CONST(DRV_DMA_TCAM_SCAN_DESC_NUM) = 33;
    /*DRV_CONST(DRV_DMA_MAX_CHAN_ID);*/

    DRV_CONST(DRV_FLOWPORTTYPE_BITMAP)                      = 0x0;
    DRV_CONST(DRV_FLOWPORTTYPE_GPORT)                       = 0x1;
    DRV_CONST(DRV_FLOWPORTTYPE_LPORT)                       = 0x2;
    DRV_CONST(DRV_FLOWPORTTYPE_METADATA)                    = 0x3;

    DRV_CONST(DRV_VTAGACTIONTYPE_NONE)                      = 0x0;
    DRV_CONST(DRV_VTAGACTIONTYPE_MODIFY)                    = 0x1;
    DRV_CONST(DRV_VTAGACTIONTYPE_ADD)                       = 0x2;
    DRV_CONST(DRV_VTAGACTIONTYPE_DELETE)                    = 0x3;

    DRV_CONST(DRV_GEMHASHTYPE_PORT)                         = 0x1;

    DRV_CONST(DRV_IPFIXHASHTYPE_INVALID)                    = 0x0;
    DRV_CONST(DRV_IPFIXHASHTYPE_L2)                         = 0x1;
    DRV_CONST(DRV_IPFIXHASHTYPE_L2L3)                       = 0x2;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3IPV4)                     = 0x3;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3IPV6)                     = 0x4;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3MPLS)                     = 0x5;

    DRV_CONST(DRV_MPLSHASHTYPE_LABEL)                       = 0x0;

    DRV_CONST(DRV_OAMHASHTYPE_ETH)                          = 0x0;
    DRV_CONST(DRV_OAMHASHTYPE_BFD)                          = 0x1;
    DRV_CONST(DRV_OAMHASHTYPE_MPLSLABEL)                    = 0x2;
    DRV_CONST(DRV_OAMHASHTYPE_MPLSSECTION)                  = 0x3;
    DRV_CONST(DRV_OAMHASHTYPE_RMEP)                         = 0x4;

    DRV_CONST(DRV_FIBHOST0HASHTYPE_FCOE)                    = 0x0;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV4)                    = 0x1;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV6MCAST)               = 0x2;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV6UCAST)               = 0x3;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_MAC)                     = 0x4;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_MACIPV6MCAST)            = 0x5;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_TRILL)                   = 0x6;

    DRV_CONST(DRV_FIBHOST1HASHTYPE_FCOERPF)                 = 0x0;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4MCAST)               = 0x1;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATDAPORT)           = 0x2;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATSAPORT)           = 0x3;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6MCAST)               = 0x4;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATDAPORT)           = 0x5;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATSAPORT)           = 0x6;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV4MCAST)            = 0x7;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV6MCAST)            = 0x8;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_TRILLMCASTVLAN)          = 0x9;
    DRV_CONST(DRV_FIB_HOST0_CAM_NUM)        = 32;
    DRV_CONST(DRV_FIB_HOST1_CAM_NUM)        = 32;
    DRV_CONST(DRV_FLOW_HASH_CAM_NUM)        = 32;
    DRV_CONST(DRV_USER_ID_HASH_CAM_NUM)     = 32;
    DRV_CONST(DRV_MPLS_HASH_CAM_NUM)        = 64;
    DRV_CONST(DRV_OAM_HASH_CAM_NUM)         = 64;
    DRV_CONST(DRV_RMEP_HASH_CAM_NUM)        = 32;
    DRV_CONST(DRV_GEM_PORT_HASH_CAM_NUM)    = 64;

    DRV_CONST(DRV_MAX_LPM_TCAM_NUM)       = 12;
    DRV_CONST(DRV_MAX_NOR_TCAM_NUM)       = 19;
    DRV_CONST(DRV_EPE_DISCARD_TYPE_NUM)   = 56;
    DRV_CONST(DRV_KEY_METADATA_BITS)      = 14;

    DRV_CONST(DRV_PARSER_L4_TYPE_UDP)       = 2;
    DRV_CONST(DRV_PARSER_L4_TYPE_GRE)       = 3;
    DRV_CONST(DRV_PARSER_L4_TYPE_TCP)       = 1;
    DRV_CONST(DRV_PARSER_L4_USER_TYPE_UDP_VXLAN)    = 5;

    DRV_CONST(DRV_EGRACL_L3K160_SHAREFIELDS_L4PORT_RNG_BMP) = 0;
    DRV_CONST(DRV_EGRACL_L3K160_SHAREFIELDS_DEFAULT)        = 3;

    DRV_CONST(DRV_DIAG_MAC_HASH_WIDTH)      = 85;
    DRV_CONST(DRV_DIAG_IPV4_HASH_WIDTH)     = 85;
    DRV_CONST(DRV_DIAG_MPLS_HASH_WIDTH)     = 34;
    DRV_CONST(DRV_DIAG_OAM_MEP_WIDTH)       = 170;
    DRV_CONST(DRV_DIAG_APS_WIDTH)           = 163;
    DRV_CONST(DRV_DIAG_FLEX_TCAM_WIDTH)     = 80;
    DRV_CONST(DRV_DIAG_EDIT_WIDTH)          = 90;

    DRV_CONST(DRV_ACCREQ_ADDR_HOST0) = 0x04050c40;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_HOST0) = 9;
    DRV_CONST(DRV_ACCREQ_ADDR_USERID) = 0x04003B70;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_USERID) = 3;
    DRV_CONST(DRV_ACCREQ_ADDR_EGRESSXCOAM) = 0x04011d9c;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_EGRESSXCOAM) = 0;
    DRV_CONST(DRV_ACCREQ_ADDR_CIDPAIR) = 0x0094337c;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_CIDPAIRHASH) = 0;

    DRV_CONST(DRV_OAM_MEPTYPE_ETH_CCM_MEP)       =0x0;
    DRV_CONST(DRV_OAM_MEPTYPE_PBT_CCM_MEP)       =0x1;
    DRV_CONST(DRV_OAM_MEPTYPE_TRILL_BFD_MEP)     =0x2;
    DRV_CONST(DRV_OAM_MEPTYPE_FFD_MEP)           =0x3;
    DRV_CONST(DRV_OAM_MEPTYPE_CV1_MEP)           =0x4;
    DRV_CONST(DRV_OAM_MEPTYPE_BFD_MEP)           =0x5;
    DRV_CONST(DRV_OAM_MEPTYPE_ACH_Y1731_MEP)     =0x6;
    DRV_CONST(DRV_OAM_MEPTYPE_ACH_BFD_MEP)       =0x7;

    DRV_CONST(DRV_DsDesc_done_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_done_f_START_BIT) = 31;
    DRV_CONST(DRV_DsDesc_done_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_START_BIT) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_memAddr_f_START_WORD) = 2;
    DRV_CONST(DRV_DsDesc_memAddr_f_START_BIT) = 4;
    DRV_CONST(DRV_DsDesc_memAddr_f_BIT_WIDTH) = 28;
    DRV_CONST(DRV_DsDesc_realSize_f_START_WORD) = 1;
    DRV_CONST(DRV_DsDesc_realSize_f_START_BIT) = 16;
    DRV_CONST(DRV_DsDesc_realSize_f_BIT_WIDTH) = 16;
    DRV_CONST(DRV_DsDesc_cfgSize_f_START_WORD) = 1;
    DRV_CONST(DRV_DsDesc_cfgSize_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_cfgSize_f_BIT_WIDTH) = 16;
    DRV_CONST(DRV_DsDesc_dataStruct_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_dataStruct_f_START_BIT) = 8;
    DRV_CONST(DRV_DsDesc_dataStruct_f_BIT_WIDTH) = 6;
    DRV_CONST(DRV_DsDesc_reserved0_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_reserved0_f_START_BIT) = 7;
    DRV_CONST(DRV_DsDesc_reserved0_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_error_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_error_f_START_BIT) = 28;
    DRV_CONST(DRV_DsDesc_error_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_chipAddr_f_START_WORD) = 3;
    DRV_CONST(DRV_DsDesc_chipAddr_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_chipAddr_f_BIT_WIDTH) = 32;
    DRV_CONST(DRV_DsDesc_pause_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_pause_f_START_BIT) = 17;
    DRV_CONST(DRV_DsDesc_pause_f_BIT_WIDTH) = 1;

    DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE) = 12;
    DRV_CONST(DRV_HOST0_DOUBLE_KEY_BYTE) = 24;
    DRV_CONST(DRV_HOST0_QUAD_KEY_BYTE)   = 48;
    DRV_CONST(DRV_NAT_TCAM_AGING_BASE) = 4096;

    DRV_CONST(DRV_MIRROR_INGRESS_L2SPAN_DISCARD) = 0x1;
    DRV_CONST(DRV_MIRROR_INGRESS_L3SPAN_DISCARD) = 0x2;
    DRV_CONST(DRV_MIRROR_INGRESS_ACLLOG_PRI_DISCARD) = 0x3FC;
    DRV_CONST(DRV_MIRROR_INGRESS_IPFIX_MIRROR_DISCARD) = 0x800;
    DRV_CONST(DRV_MIRROR_EGRESS_L2SPAN_DISCARD) = 0x1;
    DRV_CONST(DRV_MIRROR_EGRESS_L3SPAN_DISCARD) = 0x2;
    DRV_CONST(DRV_MIRROR_EGRESS_ACLLOG_PRI_DISCARD) = 0x1C;
    DRV_CONST(DRV_MIRROR_EGRESS_IPFIX_MIRROR_DISCARD) = 0x40;
    return 0;
}
extern int32
drv_tm_ftm_api_init(uint8 lchip);

static drv_mchip_sdb_t drv_sdb_api =
{
    drv_sdb_store
};
int32
drv_tbls_list_init_duet2(uint8 lchip)
{
   uint8 i = 0;
    uint16 tbl_idx = 0;

    p_drv_master[lchip]->p_tbl_ext_info = (tables_ext_info_t*)mem_malloc(MEM_SYSTEM_MODULE, (MaxTblId_t+1)*sizeof(tables_ext_info_t));
    if(!p_drv_master[lchip]->p_tbl_ext_info)
    {
        return -1;
    }
    sal_memset(p_drv_master[lchip]->p_tbl_ext_info, 0, (MaxTblId_t+1)*sizeof(tables_ext_info_t));

    p_drv_master[lchip]->p_tbl_mapping = (uint16*)mem_malloc(MEM_SYSTEM_MODULE, MaxTblId_t*sizeof(uint16));
    if(!p_drv_master[lchip]->p_tbl_mapping)
    {
        return -1;
    }

    p_drv_master[lchip]->p_tbl_info = drv_dt2_tbls_list;
    for (tbl_idx = 0; tbl_idx < MaxTblId_t; tbl_idx++)
    {
        p_drv_master[lchip]->p_tbl_mapping[tbl_idx] = (sizeof(drv_dt2_tbls_list)/sizeof(tables_info_t) -1);
    }
    for (tbl_idx = 0; tbl_idx < (sizeof(drv_dt2_tbls_list)/sizeof(tables_info_t) - 1); tbl_idx++)
    {
        p_drv_master[lchip]->p_tbl_mapping[p_drv_master[lchip]->p_tbl_info[tbl_idx].tbl_id] = tbl_idx;
    }
#ifndef DRV_DS_LITE
    p_drv_master[lchip]->p_tbl_name = drv_dt2_tbls_name_list;
#endif
    p_drv_master[lchip]->p_mem_info = drv_dt2_mem;
    drv_mem_init_dt2(lchip);

    p_drv_master[lchip]->drv_ecc_data.p_intr_tbl = drv_ecc_dt2_err_intr_tbl;
    p_drv_master[lchip]->drv_ecc_data.p_sbe_cnt  = drv_ecc_dt2_sbe_cnt;
    p_drv_master[lchip]->drv_ecc_data.p_scan_tcam_tbl = drv_ecc_dt2_scan_tcam_tbl;

    p_drv_master[lchip]->drv_mem_get_edram_bitmap = sys_duet2_ftm_get_edram_bitmap;

    p_drv_master[lchip]->drv_get_mcu_lock_id = drv_duet2_get_mcu_lock_id;
    p_drv_master[lchip]->drv_get_mcu_addr = drv_duet2_get_mcu_addr;

    p_drv_master[lchip]->drv_chip_read_hss15g = drv_duet2_chip_read_hss15g;
    p_drv_master[lchip]->drv_chip_write_hss15g = drv_duet2_chip_write_hss15g;
    p_drv_master[lchip]->drv_chip_read_hss28g = drv_duet2_chip_read_hss28g;
    p_drv_master[lchip]->drv_chip_write_hss28g = drv_duet2_chip_write_hss28g;
    p_drv_master[lchip]->mchip_api.p_mchip_sdb = &drv_sdb_api;

    p_drv_master[lchip]->p_enum_value = drv_dt2_enum;
    p_drv_master[lchip]->p_tcam_map = drv_dt2_tcam_mem_map;
    p_drv_master[lchip]->drv_io_tcam_db = drv_dt2_io_tcam_db;


    for (i = 0; i < DRV_IO_TCAM_TYPE_NUM; i++)
    {
        p_drv_master[lchip]->drv_io_tcam_db[i].drv_tcam_get_block_info = drv_dt2_tcam_get_blknum_index;

#if (1 == SDK_WORK_PLATFORM)
        p_drv_master[lchip]->drv_io_tcam_db[i].hw_words = drv_dt2_io_tcam_db[i].tcam_mem_tbl_id? TABLE_INFO(lchip, drv_dt2_io_tcam_db[i].tcam_mem_tbl_id).byte/4:0;
#endif
    }

    p_drv_master[lchip]->drv_io_tcam_db[DRV_IO_TCAM_TYPE_FLOW].drv_tcam_get_block_info = drv_flow_tcam_get_blknum_index;

    drv_enum_init_duet2(lchip);
    drv_tm_ftm_api_init(lchip);

    return 0;
}

int32
drv_tbls_list_deinit_duet2(uint8 lchip)
{
    if(p_drv_master[lchip]->p_tbl_ext_info)
    {
        mem_free(p_drv_master[lchip]->p_tbl_ext_info);
    }
    if(p_drv_master[lchip]->p_tbl_mapping)
    {
        mem_free(p_drv_master[lchip]->p_tbl_mapping);
    }
    return 0;
}


#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_C
#undef DRV_DEF_E
#undef DRV_DEF_SDK_F
#undef DRV_DEF_SDK_D


#endif
